The present invention relates, in general, to dynamic random access memories (DRAMs) and, more particularly, to a DRAM having synchronized control timing.
Various types of DRAMs are known in the industry. Access to the DRAM (reading and writing information) is generally controlled by a DRAM Controller. When access is to be made, the controller sends a Row Address Strobe (RAS) and a Column Address Strobe (CAS) to select the particular bit that is to be accessed. The timing of the controller output is based on the input from a system clock.
As DRAM speeds increase, it is becoming more difficult for memory system designers to use the available speed due to problems related to generating the necessary timing signals. This is particularly true of page mode cycle times (where several column addresses are sequentially provided for a single row address).
In a computer system, there is a system clock which is used to clock the processor and other peripheral circuitry which in turn generate the necessary timing signals for the memory system. Since the timing signals to the DRAM are processed through other logic devices prior to reaching the DRAM, the resulting signals will have delays (skews) with respect to other signals and the system clock. Further, these skews will be different for each signal since the signals are processed through different circuitry. Because of these skews, designers must allow for extra time in the signal lengths. The result of having to add 6-8 ns to a 40 ns signal is quite substantial.
Therefore, there exists a need in the industry for a memory system that will reduce or eliminate the skew associated with processing of timing signals.
Accordingly, it is an objective of the present invention to provide a DRAM which overcomes the above deficiencies.
Another object of the present invention is to reduce the skew associated with the row and column address strobes (RAS and CAS).
Still another object of the present invention is to provide a DRAM having synchronized control timing.
Yet another object of the present invention is to provide a DRAM having control timing synchronized with a clock input.